module alu(a, b, op, z, s); input [31:0] a, b; input [2:0] op; output z; output [31:0] s; reg [31:0] s; reg [31:0] addsub; always @(a or b or op[2]) begin if (op[2]) addsub <= a - b; else addsub <= a + b; end always @(a or b or op or addsub) begin case (op) 3'b000: s <= a & b; 3'b001: s <= a | b; 3'b010: s <= addsub; 3'b110: s <= addsub; 3'b111: s <= {31'h0, addsub[31]}; default: s <= 32'hxxxxxxxx; endcase end assign z = (s == 32'h0); endmodule // alu