module regfile(clk, rst, a_addr, b_addr, a_dout, b_dout, w_addr, w_din, we); input clk, rst; input [4:0] a_addr, b_addr; output [31:0] a_dout, b_dout; input [4:0] w_addr; input [31:0] w_din; input we; reg [31:0] regmem [0:31]; integer i; always @(posedge clk or negedge rst) begin if (!rst) begin for (i = 0; i < 32; i = i + 1) regmem[i] <= 32'h0; end else if (we) regmem[w_addr] <= w_din; end assign a_dout = regmem[a_addr]; assign b_dout = regmem[b_addr]; endmodule